For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.
Semiconductor devices formed from group III-V compound semiconductor material systems offer exceptionally high carrier mobility in the transistor channels due to low effective mass along with reduced impurity scattering. Group III and group V refer to a location of the elements of the semiconductor material in groups 13-15 of the Periodic Table of Elements (formerly groups III-V). Such devices provide high drive current performance and appear promising for future low power, high-speed logic applications. To integrate such materials on a silicon substrate, buffer layer(s) of relatively wider band gap material are typically introduced between the silicon and the group III-V compound channel material to confine carriers to the channel material and achieve short channel effects in the buffer layer(s).